1. Field of the Invention
The invention relates to design of layouts used in fabrication of semiconductor wafers. More specifically, the invention relates to a method and an apparatus for rule-based detection of pinches, bridges and similar hot spot regions in wires of an integrated circuit (IC) chip and repair of the regions.
2. Related Art
In the manufacture of integrated circuit (IC) chips, minimum feature sizes have been shrinking according to Moore's law. Currently the minimum feature size is smaller than the wavelength of light used in the optical imaging system. Accordingly it has become increasingly difficult to achieve reasonable fidelity (including resolution and depth of focus) between (a) a layout as designed in a computer and (b) shapes of circuit elements formed in a wafer after fabrication, which normally involves a number of processes such as photolithography followed by metal deposition and chemical mechanical polishing.
One prior art data flow in designing a layout is described in an article entitled “Hotspot detection on post-OPC layout using full-chip simulation-based verification tool: a case study with aerial image simulation” by Juhwan Kim and Minghui Fan, Proc. SPIE 5256, 919 (2003) that is incorporated by reference herein in its entirety. During such a prior art data flow, a place and route step 101 is typically followed by a step 102 of optical rule checking (ORC) which can take one or more days (e.g. more than 24 hours). A result of place and route step 101 is a layout of the type shown in FIG. 1B. This illustrative layout has three metal traces 111-113 which are arranged in a staircase pattern relative to one another.
Prior art ORC in step 103 is performed on a layout globally (to the knowledge of the inventors), and it includes resizing of the layout, followed by OPC on the resized layout, followed by simulation of lithographic processes to obtain image intensity, followed by evaluation of contours in the image intensity, as discussed in the next paragraph. Note that the result of ORC is the location of hot spots in a layout. The identified hot spots are typically fixed manually, in some prior art techniques. Manual fixing of hot spots is slow and laborious. Moreover, use of ORC to detect hot spots is itself slow.
Specifically, ORC includes a resizing (or upsizing) operation in which the width and length of rectangles are increased, if certain rules are satisfied (e.g. if minimum spacing constraints imposed in DRC rules are not violated). For more information on such operations, see an article entitled “Logic design for printability using OPC methods” by Lucas, K.; Yuan, C.-M.; Boone, R.; Wimmer, K.; Strozewski, K.; Toublan, O. published in Design & Test of Computers, IEEE, Volume 23, Issue 1, January-February 2006 Page(s):30-37, which is incorporated by reference herein in its entirety.
After such resizing (or upsizing), during an OPC operation within ORC, any reticle enhancement technology (RET) technique may be used, such as optical proximity correction (OPC), use of phase shifting masks (PSM) and/or sub-resolution assist features (SRAF). FIG. 1C illustrates shapes 121-123 which replace the respective traces 111-113 in FIG. 1B for use in fabrication. The following two articles have attempted to quantify the amount of RET (e.g. in the form of OPC) that a routed layout requires and modify the routing such that the burden of mask synthesis tools is reduced: [1] L-D. Huang, M. D. F. Wong: Optical Proximity Correction (OPC)-Friendly Maze Routing, DAC 2004; and [2] J. Mitra, P. Yu, D. Pan: RADAR: RET-aware detailed routing using fast lithography simulations, DAC 2005. These two articles are incorporated by reference herein in their entirety.
A wafer which is fabricated by use of the OPC-corrected layout in FIG. 1C may still have one or more defects. For example, FIG. 1D shows a fabricated layout including metal traces 131-133 wherein a trace 132 has a width Wpinch, which is significantly smaller than the nominal width W of corresponding trace 112 in the placed and routed layout of FIG. 1B. If Wpinch falls below a minimum limit, it causes an open circuit failure in the IC chip. Although a pinching defect has been illustrated in FIG. 1D, a similar bridging defect is also possible where, e.g., trace 132 merges enough with trace 131 to cause a short circuit failure in the IC chip. Such defects in the fabricated layout are commonly called “hot spots.” To ensure that silicon produced with sub-wavelength geometries functions as intended in the original layout, one may use a layout verification tool. For example, a tool called SiVL-LRC available from Synopsys, Inc. reads in the IC layout and simulates a lithographic process, including optical, resist and etch effects, to generate an image intensity. Contours in the image intensity formed by a predefined threshold are then evaluated relative to the intended layout, and out of-tolerance regions are reported. Evaluation of contours of image intensity can be performed in any manner, e.g. by measurement of critical dimension and/or gradient of image intensity.
Note that the operations, (i) OPC that a particular layout needs for fabrication at a particular wavelength of light and (ii) simulation by SiVL-LRC to generate the silicon image followed by layout verification, normally take several days of simulation time for a 1-million gate design, when using a computer (e.g. PC) with a central processing unit (CPU) operating at 2 GHz and equipped with 1 GB memory. At this stage, if there are no defects that need correction, the layout is taped out in step 104, followed by step 105 in which a mask is synthesized for use in fabrication of semiconductor wafers. Current technology (prior to the invention described below) addresses any issues found by ORC in step 103 by application of design rules that are typically specified by a fabrication facility (“fab”) and returning to step 102. However, use of fab-specified design rules can result in over-specification of a design or an unnecessarily large number of defects from fabrication thereby reducing yield.
A commonly-owned and co-pending U.S. patent application Ser. No. 11/394,466 filed on Mar. 31, 2006 and entitled “A RANGE PATTERN DEFINITION OF SUSCEPTIBILITY OF LAYOUT REGIONS TO FABRICATION ISSUES” by Subarnarekha Sinha et al. is incorporated by reference herein in its entirety. Also incorporated by reference herein in its entirety is another commonly-owned and co-pending U.S. patent application Ser. No. 11/395,006 filed on Mar. 31, 2006 and entitled: “IDENTIFYING LAYOUT REGIONS SUSCEPTIBLE TO FABRICATION ISSUES BY USING RANGE PATTERNS” by Subarnarekha Sinha et al.